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Tutorial Project: Pico-Based Oscilloscope/Logic Analyzer (Picotronix-Inspired)

Purpose​

Create a team tutorial project that learns from the Picotronix (dual-Pico) architecture and builds a simplified prototype:

  • 2-channel scope (starter)
  • basic logic analyzer (optional)
  • a clear message protocol between a Data MCU and a Control/UI MCU

This is explicitly a learning project focused on:

  • high-speed sampling constraints
  • partitioning time-critical capture from UI/networking
  • structured datagram protocols

References​

Why this project is valuable​

Key ideas worth copying into your own designs:

  • Two MCU split: one MCU dedicated to data acquisition (tight timing), one for UI + comms.
  • Datagram protocol: structured messages instead of ad-hoc commands (better extensibility).
  • Optional display: can run headless and stream to PC/phone.

Scope​

In scope (MVP)​

  • Hardware: 2x Raspberry Pi Pico (Pico 2 if available)
  • Data MCU:
    • capture ADC samples (single channel first)
    • stream frames over UART
  • Control MCU:
    • receive frames
    • render a minimal waveform view on serial plotter or a tiny local display (optional)
    • forward to PC via USB serial
  • Protocol:
    • sync word + length + payload (binary)
    • payload encoded as msgpack (or CBOR) key/value map

Out of scope (for MVP)​

  • 20 MHz analog front-end design and calibration
  • Advanced trigger modes
  • High speed effective sampling tricks (ESR) beyond a basic note

Suggested architecture (Picotronix-inspired)​

MCU roles​

  • Data Pico (time-critical)

    • ADC sampling + DMA
    • optional PIO timing for digital capture
    • outputs frames

  • Control Pico

    • user input + display/network
    • sends capture commands
    • receives frames and forwards to PC

Message protocol (starter)​

Use a robust framing format (from Picogram idea):

  • SYNC (4 bytes) fixed magic
  • LEN (2 bytes) payload length
  • PAYLOAD (msgpack/CBOR)

For MVP you can keep payload simple:

  • msg_id
  • op ("capture", "set_rate", "ping")
  • rate_hz
  • samples
  • channel
  • response includes op_result + sample blob

Bring-up plan (harness gates)​

Gate 0 — Toolchain​

  • Pico SDK / PlatformIO setup
  • Build + flash hello-blinky for both boards

Gate 1 — Control/Data link​

  • UART link at a chosen baud (start 921600 or lower if unstable)
  • "ping" request → "pong" response

Gate 2 — Packet framing works​

  • Send framed messages with SYNC+LEN
  • Validate receiver can resync after noise

Gate 3 — ADC capture (single channel)​

  • Capture N samples
  • Return in payload
  • Verify waveform matches a known signal (function generator)

Gate 4 — PC-side viewer​

  • A small Python script parses frames and plots waveform

Gate 5 — Optional extras​

  • Add second channel
  • Add simple trigger
  • Add digital capture stub

Deliverables​

  • docs/ARCHITECTURE.md (dual MCU partition)
  • docs/PROTOCOL.md (frame format + msgpack schema)
  • Firmware for Data Pico (capture)
  • Firmware for Control Pico (command + forward)
  • Python viewer script
  • Lab validation checklist

Suggested team roles​

  • Firmware A: Data Pico capture
  • Firmware B: Control Pico protocol + forwarding
  • Tools: Python viewer
  • Docs: protocol + bring-up checklist

Notes from the references (useful details)​

From the Picotronix writeups:

  • Logic capture can use PIO state machines; practical throughput mentioned around ~100MB/s internal transfer.
  • A simple but robust packet protocol uses a high-entropy sync word + length field.
  • msgpack makes it easy to support multiple hosts and languages.

Changelog​

  • 2026-02-14: Created tutorial project page.