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RAK3112 AS923 Dev Board — PCB Spec (v1)

This document is the implementation-ready PCB specification for a RAK3112 (AS923) development board.

Design intent:

  • external USB-UART dongle flashing (no onboard USB-UART)
  • power flexibility: 9–12V DC, Li-ion 1S + charging, regulated 5V + 3V3
  • connectors mostly Qwiic (JST-SH) and screw terminals
  • deterministic bring-up with gate checks

0) Core decisions (locked)​

  • Module: RAK3112 AS923
  • Programming: USB-UART bootloader
  • On-board programming: pin header only
  • Qwiic: 3V3 only

1) Power subsystem​

Inputs​

  • J_DC_IN (screw terminal): 9–12V DC input
  • J_BAT (JST-PH2): Li-ion 1S battery input
  • (optional) pads/testpoints for 5V bench input

Rails​

  • VIN → 5V buck (≥2A)
  • 5V → 3V3 buck (≥1A recommended; Wi-Fi peak current margin)

Charging​

  • Li-ion 1S charger (linear charger IC) with:
    • charge current set resistor
    • CHG/DONE status LEDs

Power-path / selection (choose one)​

  • Preferred: power-path / ideal diode ORing so board can run while charging
  • Acceptable v1: diode ORing + source-select jumper

Jumpers​

  • JP_3V3_EN: enable/cut 3V3 to module (debug + current measurement)
  • JP_VBAT_SENSE: enable VBAT divider to ADC (avoid battery drain)

Test points​

  • TP_VIN, TP_5V, TP_3V3, TP_VBAT, TP_GND

2) Programming + boot header (external USB-UART dongle)​

J_PROG (1×6, 2.54mm)​

PinSignalNotes
1GNDCommon ground
23V3Reference / optional power-out
3UART0_RXModule UART0_RX (to dongle TX)
4UART0_TXModule UART0_TX (to dongle RX)
5BOOT_SELBoot strap input (see SJ_BOOT_SRC)
6RESETActive-low reset

Boot selection​

The docs show GPIO0/Boot and also a GPIO46 pin. To be safe, support both:

  • SJ_BOOT_SRC solder jumper:
    • position A: BOOT_SEL → GPIO0/Boot
    • position B: BOOT_SEL → GPIO46

Boot strap components:

  • BOOT default: 10k pulldown
  • BOOT button or 2-pin jumper to 3V3 for flashing

Reset components:

  • RESET: 10k pull-up to 3V3
  • RESET button to GND

3) I2C (Qwiic)​

I2C2 (default sensor bus)​

Locked from pin tables:

  • SCL = GPIO18 (I2C2_SCL)
  • SDA = GPIO17 (I2C2_SDA)

Provide:

  • J_QWIIC_1, J_QWIIC_2 (JST-SH 4-pin) in parallel
    • GND / 3V3 / SDA(GPIO17) / SCL(GPIO18)

Pullups:

  • JP_I2C2_PU: enable pullups (4.7k to 3V3)

I2C1 (optional secondary bus)​

From pin tables:

  • SDA = GPIO09 (I2C1_SDA)
  • SCL = GPIO40 (I2C1_SCL)

If included:

  • 1× Qwiic or JST-GH header
  • JP_I2C1_PU pullups

4) SPI​

From pin tables:

  • MISO = GPIO10
  • MOSI = GPIO11
  • CS = GPIO12
  • SCK = GPIO13

Connector:

  • J_SPI (1×7 pin header or JST-GH): GND, 3V3, MISO, MOSI, SCK, CS, GPIO8(optional IRQ)

5) Analog inputs​

From pin tables/module map:

  • AIN0 = GPIO21
  • AIN1 = GPIO14

Connector:

  • J_AIN (screw terminal): 3V3, GND, AIN0(GPIO21), AIN1(GPIO14)

Per-channel protection footprint:

  • series resistor (1k)
  • optional RC filter
  • optional clamp diode footprint

6) GPIO breakouts​

Provide 2–3 JST-GH headers:

  • J_GPIO_A: GND, 3V3, GPIO1, GPIO2, GPIO3, GPIO8
  • J_GPIO_B: GND, 3V3, GPIO38, GPIO39, GPIO41, GPIO42
  • J_GPIO_C (optional): GND, 3V3, GPIO45, GPIO46, GPIO21, GPIO14

Add series resistor footprints (0–100Ω) for each GPIO.

Optional / 16MB flash dependent GPIOs (NC*)​

The docs indicate some GPIOs may be unavailable (marked NC* in pin tables) with 16MB flash variants:

  • GPIO33, GPIO34, GPIO35, GPIO36, GPIO37

If exposed, put them on a separate header clearly labeled:

  • J_GPIO_OPT: GND, 3V3, GPIO33, GPIO34, GPIO35, GPIO36/37

7) Indicators​

  • RGB LED (discrete, 3 channels + resistors)
  • PWR LED (3V3)
  • STATUS LED (GPIO)

8) RF/layout notes​

  • Follow RAK reference design keepouts.
  • Keep DC-DC switching nodes away from RF.
  • If adding u.FL/SMA, place close to RF pins; controlled impedance.

9) Bring-up gates​

  • Gate 0: Schematic ERC clean; pin map verified vs datasheet
  • Gate 1: VIN→5V→3V3 stable under load; battery charging verified
  • Gate 2: Bootloader entry (BOOT + RESET) + flash via external USB-UART
  • Gate 3: UART logs stable
  • Gate 4: I2C2 scan on Qwiic (GPIO17/18)
  • Gate 5: SPI peripheral or loopback (GPIO10/11/12/13)
  • Gate 6: ADC validation (GPIO21/14)
  • Gate 7: LoRa AS923 join + uplink; Wi-Fi join test